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M69AW024B
16 Mbit (1M x16) 3V Asynchronous PSRAM
FEATURES SUMMARY

SUPPLY VOLTAGE: 2.7 to 3.3V ACCESS TIME: 60ns, 70ns LOW STANDBY CURRENT: 70A DEEP POWER DOWN CURRENT: 10A LOW VCC DATA RETENTION: 2.3V COMPATIBLE WITH STANDARD LPSRAM
Figure 1. Package
BGA
TFBGA48 (ZB) 6x8 mm
September 2004
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M69AW024B
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable (E2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Upper Byte Enable (UB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lower Byte Enable (LB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... .....6 .....6 .....6 .....6 .....6 .....6 .....6 .....6 .....6 .....6 .....6 .....7 .....8
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power On Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Deep Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 4. Figure 5. Figure 6. Table 5. Table 6. Table 7. Figure 7. Figure 8. Figure 9. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Read and Standby Modes AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output Enable Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chip Enable Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Address Access After G Control, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . 16
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Figure 10.Address Access After E1 Control, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . 16 Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 11.E1 Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 12.W Controlled, Single Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 13.W Controlled, Continuous Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 14.E1 Controlled, Read/Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 15.E1 Controlled, Read/Write AC Waveforms 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 16.G Controlled Read, W Controlled Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 17.G Controlled Read, W Controlled Write AC Waveforms 2 . . . . . . . . . . . . . . . . . . . . . . . 22 Table 9. Power Down and Power-Up AC Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 18.Standby Mode Entry AC Waveforms, After Read or Write . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 19.Power-down AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 20.Power-up Mode AC Waveforms - 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 21.Power-up Mode AC Waveforms - 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 22.Power-up Mode AC Waveforms - 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 10. Low VCC Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 23.Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 24.TFBGA48 6x8mm - 6x8 Ball Array, 0.75mm Pitch, Package Outline, Bottom View . . . . 26 Table 11. TFBGA48 6x8mm - 6x8 Ball Array, 0.75mm Pitch, Package Mechanical Data. . . . . . . . 26 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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M69AW024B
SUMMARY DESCRIPTION
The M69AW024B is a 16 Mbit (16,777,216 bit) CMOS memory, organized as 1,048,576 words by 16 bits, and is supplied by a single 2.7V to 3.3V supply voltage range. M69AW024B is a member of STMicroelectronics PSRAM memory family, based on the one-transistor per-cell architecture. These devices are manufactured using dynamic random access memory cells, to minimize the cell size, and maximize the amount of memory that can be implemented in a given area. However, through the use of internal control logic, the device is fully static in its operation, requiring no external clocks or timing strobes, and has a standard Asynchronous SRAM Interface. The internal control logic of the M69AW024B handles the periodic refresh cycle, automatically, and without user involvement. Write cycles can be performed on a single byte by using Upper Byte Enable (UB) and Lower Byte Enable (LB). The device can be put into standby mode using Chip Enable (E1) or in deep power down mode by using Chip Enable (E2). Power-Down mode achieves a very low current consumption by halting all the internal activities. Since the refresh circuitry is halted, the duration of the power-down should be less than the maximum period for refresh, if the user has not finished with the data contents of the memory.
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A19 Address Input Data Input/Output Chip Enable, Power Down Output Enable Write Enable Upper Byte Enable Lower Byte Enable Supply Voltage Ground Not Connected (no internal connection)
VCC
DQ0-DQ15 E1, E2
20 A0-A19 W E1 E2 G UB LB M69AW024B
16 DQ0-DQ15
G W UB LB VCC VSS NC
VSS
AI07406
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Figure 3. TFBGA Connections (Top view through package)
1 2 3 4 5 6
A
LB
G
A0
A1
A2
E2
B
DQ8
UB
A3
A4
E1
DQ0
C
DQ9
DQ10
A5
A6
DQ1
DQ2
D
VSS
DQ11
A17
A7
DQ3
VCC
E
VCC
DQ12
NC
A16
DQ4
VSS
F
DQ14
DQ13
A14
A15
DQ5
DQ6
G
DQ15
A19
A12
A13
W
DQ7
H
A18
A8
A9
A10
A11
NC
AI07409
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M69AW024B
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram, and Table 1., Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A19). The Address Inputs select the cells in the memory array to access during Read and Write operations. Data Inputs/Outputs (DQ8-DQ15). The Upper Byte Data Inputs/Outputs carry the data to or from the upper part of the selected address during a Write or Read operation, when Upper Byte Enable (UB) is driven Low. Data Inputs/Outputs (DQ0-DQ7). The Lower Byte Data Inputs/Outputs carry the data to or from the lower part of the selected address during a Write or Read operation, when Lower Byte Enable (LB) is driven Low. Chip Enable (E1). When asserted (Low), the Chip Enable, E1, activates the memory state machine, address buffers and decoders, allowing Read and Write operations to be performed. When de-asserted (High), all other pins are ignored, and the device is put, automatically, in low-power Standby mode. Chip Enable (E2). The Chip Enable, E2, puts the device in Deep Power-down mode when it is driven Low. This is the lowest power mode. Output Enable (G). The Output Enable, G, provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory. Upper Byte Enable (UB). The Upper Byte Enable, UB, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-DQ15) to or from the upper part of the selected address during a Write or Read operation. Lower Byte Enable (LB). The Lower Byte Enable, LB, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-DQ7) to or from the lower part of the selected address during a Write or Read operation. VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read or Write) and for driving the refresh logic, even when the device is not being accessed. VSS Ground. The VSS Ground is the reference for all voltage measurements.
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Figure 4. Block Diagram
INTERNAL CLOCK GENERATOR ROW DECODER
ARBITRATION LOGIC REFRESH CONTROLLER VCC DYNAMIC MEMORY ARRAY
ADDRESS
DQ0-DQ7 DQ8-DQ15
E1 E2 G W LB UB VCC VSS POWER CONTROLLER CONTROL LOGIC
INPUT/OUTPUT BUFFER COLUMN DECODER
ADDRESS
AI07410
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Table 2. Operating Modes
Operation Standby (Deselect) Output Disabled (2) Output Disabled (No Read) Word Read(5) Word Read Upper Byte Write Lower Byte Write Word Write Power-down (3)
Note: 1. 2. 3. 4. 5. 6.
E2 VIH VIH VIH VIH VIH VIH VIH VIH VIL
E1 VIH VIL VIL VIL VIL VIL VIL VIL X (1)
W X (1) VIH VIH VIH VIH VIL VIL VIL X (1)
G X (1) VIH VIL VIL VIL VIH VIH VIH X (1)
LB X (1) X (1) VIH
UB X (1) X (1) VIH
A0-A19 X (1) Note (4) Valid Valid Valid Valid Valid Valid X (1)
DQ0-DQ7 Hi-Z Hi-Z Hi-Z
DQ8DQ15 Hi-Z Hi-Z Hi-Z
ICC ISB ICC ICC ICC ICC ICC ICC ICC IPD
Data Retention Yes Yes Yes Yes Yes Yes Yes Yes No
VIL(6) VIL VIH VIL VIL X (1) VIL VIL VIH VIL X (1)
Output Valid Output Valid Invalid Input Valid Input Valid Hi-Z Input Valid Invalid Input Valid Hi-Z
X = VIH or VIL. Output Disable mode should not be kept longer than 1s. Power-down mode can be entered from Stand-by state, and all DQ pins are in Hi-Z state. Can be either VIL or VIH but must be valid before Read or Write. Byte Read is not supported. Either or both LB and UB must be Low, VIL, for Read operations.
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OPERATION
Operational modes are determined by device control inputs W, E1, E2, LB and UB as summarized in the Operating Modes table (see Table 2.). Power On Sequence Because the internal control logic of the M69AW024B needs to be initialized, the following power-on procedure must be followed before the memory is used: - Apply power and wait for VCC to stabilize - Wait 400s while driving both Chip Enable signals (E1 and E2) High - Activate the memory by driving Chip Enable (E1) Low. Read Mode The device is in Read mode when: - Write Enable (W) is High and - Output Enable (G) Low and - the two Chip Enable signals are asserted (E1 is Low, and E2 is High). The time taken to enter Read mode (tELQV, tGLQV or tBLQV) depends on which of the above signals was the last to reach the appropriate level. Data out (DQ15-DQ0) may be indeterminate during tELQX, tGLQX and tBLQX, but data will always be valid during tAVQV. Write Mode The device is in Write mode when - Write Enable (W) is Low and - Chip Enable (E1) is Low and the two Chip Enable signals are asserted (E1 is Low, and E2 is High) - one of Upper Byte Enable (UB) or Lower Byte Enable (LB) is Low, while the other is High. The Write cycle begins just after the event (the falling edge) that causes the last of these conditions to become true (tAVWL or tAVEL or tAVBL). The Write cycle is terminated by the earlier of a rising edge on Write Enable (W) or Chip Enable (E1). If the device is in Write mode (Chip Enable (E1) is Low, Output Enable (G) is Low, Upper Byte Enable (UB) or Lower Byte Enable (LB) is Low), then Write Enable (W) will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable (W), or for tDVEH before the rising edge of Chip Enable (E1), whichever occurs first, and remain valid for tWHDX, tEHDX Standby Mode The device is in Standby mode when: - Chip Enable (E1) is High and - Chip Enable (E2) is High. The input/output buffers and the decoding/control logic are switched off, but the dynamic array continues to be refreshed. In this mode, the memory current consumption, ISB, is reduced, and the data remains valid. Deep Power-down Mode The device is in Deep Power-down mode when: - Chip Enable (E2 is Low). -
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MAXIMUM RATING
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are Table 3. Absolute Maximum Ratings
Symbol IO TA TSTG VCC VIO Output Current Ambient Operating Temperature Storage Temperature Core Supply Voltage Input or Output Voltage Parameter Min -50 -30 -55 -0.5 -0.5 Max 50 85 125 3.6 3.6 Unit mA C C V V
stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied.
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DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4., Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.
Table 4. Operating and AC Measurement Conditions
M69AW024B Parameter Min VCC Supply Voltage1 Ambient Operating Temperature Load Capacitance (CL) Output Circuit Protection Resistance (R1) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages Output Transition Timing Ref. Voltages Input Transition Time2 (t ) between VIL and VIH 0 to VCC VCC/2 VRL = 0.3VCC; VRH = 0.7VCC 5 2.7 -30 50 50 4 -60, -70 Max 3.3 85 V C pF ns V V V ns Unit
Note: 1. All voltages are referenced to VSS. 2. The Input Transition Time used in AC measurements is 5ns. For other input transition times, see Table 9.
Figure 5. AC Measurement Load Circuit
VCC/2
Figure 6. AC Measurement I/O Waveform
R1
I/O Timing Reference Voltage VCC
DEVICE UNDER TEST CL
OUT 0V
VCC/2
Output Timing Reference Voltage VCC 0.7VCC 0.3VCC
AI07753
0V CL includes JIG capacitance
AI07222c
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Table 5. Capacitance
Symbol CIN COUT (1) Parameter Input Capacitance on all pins (except DQ) Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 5 8 Unit pF pF
Note: 1. Outputs deselected.
Table 6. DC Characteristics
Symbol Parameter Test Condition VCC = 3.3V, VIN = VIH or VIL, E1 = VIL, E2 = VIH, IOUT = 0mA 0V VIN VCC 0V VOUT VCC VCC = 3.3V, VIN = VIH or VIL, E2 0.2V 3.1V VCC 3.3V, VIN = VIH or VIL, E1 = VIH and E2 = VIH, IOUT = 0mA 2.7V VCC 3.1V, VIN = VIH or VIL, E1 = VIH and E2 = VIH, IOUT = 0mA ISB Standby Supply Current CMOS 3.1V VCC 3.3V, VIN 0.2V or VCC -0.2V, E1 VCC -0.2V and E2 VCC -0.2V), IOUT = 0mA 2.7V VCC 3.1V, VIN 0.2V or VCC -0.2V, E1 VCC -0.2V and E2 VCC -0.2V), IOUT = 0mA VIH (2) 3.1V VCC 3.3V Input High Voltage 2.7V VCC 3.1V 3.1V VCC 3.3V Input Low Voltage 2.7V VCC 3.1V 3.1V VCC 3.3V, IOH = -0.5mA Output High Voltage Output Low Voltage 2.7V VCC 3.1V, IOH = -0.5mA VCC = 3V, IOL = 1mA 2.6 2.2 -0.3 -0.3 2.5 2.2 0.4 tRC/tWC = Min tRC/tWC = 1s -1 -1 Min Max 20 3.0 1 1 Unit mA mA A A
ICC1
(1)
Operating Supply Current
ILI ILO
Input Leakage Current Output Leakage Current Deep Power Down Current
IPD
10
A
1.5
mA
1
mA
100
A
70
A
VCC + 0.3 VCC + 0.3 0.6 0.5
V V V V V V V
VIL (3)
VOH VOL
Note: 1. Average AC current, Outputs open, cycling at tAVAX (min). 2. Maximum DC voltage on input and I/O pins is VCC + 0.3V. During voltage transitions, input may positive overshoot to VCC + 1.0V for a period of up to 5ns. 3. Minimum DC voltage on input or I/O pins is -0.3V. During voltage transitions, input may positive overshoot to VSS + 1.0V for a period of up to 5ns.
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Table 7. Read and Standby Modes AC Characteristics
M69AW024B Symbol Alt. Parameter -60 Min tAVAX tAVEH tAVEL(5) tAVGH tAVGL1(3,6) tAVGL2(7) tAVQV(1,4) tAXAV(4,8) tAXQX(1) tBLEL(5) tBLGL tEHAX tEHBH tEHEL tEHQX(1) tEHQZ(2) tELAX(4) tELEH tELGH tELGL(3,6,9,10) tELQV(1,3) tELQX(2) tGHAX tGHBH tGHGL1(6,9,10) tGHGL2(7) tGHQX(1) tGHQZ(2) tGLAX(4,9) tGLEH(9) tRC tRC tASC tRC tASO Read Cycle Time Address Valid to Chip Enable High (Read Cycle Time) Address Set-up Time to Chip Enable Low Address Valid to Output Enable High (Read Cycle Time) Address Valid to Output Enable Low 80 80 -5 80 25 5 60 5 5 -5 0 -5 -5 10 5 20 80 80 80 25 1000 60 5 -5 -5 25 10 5 20 45 45 50 50 1000 5 -5 -5 30 10 5 25 1000 90 90 90 30 1000 70 5 -5 0 -5 -5 12 5 25 Max -70 Min 90 90 -5 90 30 5 70 5 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tASO(ABS) Address Valid to Output Enable Low (absolute) tAA tAX tOH tBSC tBSO tCHAH tCHBH tCP tOH tCHZ tCLAH tRC tRC tCLOL tCE tCLZ tOHAH tOHBH tOP tOP(ABS) tOH tOHZ tOLAH tOLCH Address Access Time Address Invalid Time Output Hold Time after Address Transition LB, UB Set-up Time to Chip Enable Low LB, UB Set-up Time to Output Enable Low Chip Enable High to Address Hold Time Chip Enable High to LB, UB High Chip Enable High Pulse Width Output Hold Time after Chip Enable Low Chip Enable High to Output Hi-Z Chip Enable Low to Address Hold Time Chip Enable Low to Chip Enable High (Read Cycle Time) Chip Enable Low to Output Enable High (Read Cycle Time) Chip Enable Low to Output Enable Low Delay Time Chip Enable Access Time Chip Enable Low to Output Lo-Z Output Enable High to Address Hold Time Output Enable High to LB, UB High Output Enable High Pulse Width Output Enable High Pulse Width (absolute) Output Hold Time after Output Enable Low Output Enable High to Output Hi-Z Output Enable Low to Address Hold Time Output Enable Low to Chip Enable High Delay Time
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M69AW024B
M69AW024B Symbol Alt. Parameter -60 Min tGLQV(1) tGLQX(2) tOE tOLZ Output Enable Access Time Output Enable Low to Output Lo-Z 0 Max 35 0 -70 Min Max 40 ns ns Unit
Note: 1. CL = 50pF with 1 TTL and R1=50. 2. CL = 5pF 3. tELQV is applicable if G is brought to Low before E1 goes Low and if actual value of either tAVGL1 or tELGL, or both, is shorter than the specified value. 4. Only applicable to A0, A1 and A2 when both and G and E1 are kept Low for Address access. 5. Applicable if G is brought to Low before E1 goes Low. 6. tAVGL1, tELGL(Min) and tGHGL1(Min) are reference values when the access time is determined by tGLQV. If the actual value of each parameter is lower than the specified minimum values, tGLQV is increased by the difference between the actual value and the specified minimum value. 7. tAVGL2 and tGHGL2 correspond to absolute minimum values during G controlled access. 8. tAXAV is applicable when two or more addresses from A0 to A2 are switched from the previous state. 9. If the actual value of tELGL or tGHGL1 is lower than the specified minimum value, tGLAX and tGLEH will be equal to tAVAX(Min) - tELGL (Actual) and tAVAX (Min) -tGHGL1 (Actual), respectively. 10. The maximum value is applicable if E1 is kept Low.
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M69AW024B
Figure 7. Output Enable Controlled, Read Mode AC Waveforms
A0-A19 ADDRESS VALID tGHAX tELGH tELQV E1 tELGL tAVGL1 G tBLGL LB, UB tGHQZ tGLQX DQ0-DQ15 tGHQX VALID tGHQZ tGLQX tGHQX VALID
AI07743
ADDRESS VALID tGHAX tAVGH tAVGL2
tGLQV tGHGL1
tGLEH tGLQV
tGHBH
tBLGL
tGHBH
Note: 1. E2 = High and W = High. 2. Either or both LB and UB must be Low when both E1 and G are Low.
Figure 8. Chip Enable Controlled, Read Mode AC Waveforms
A0-A19
ADDRESS VALID tELEH tAVEL tELQV tEHAX
ADDRESS VALID tELEH tAVEL tELQV tEHAX
E1 tEHEL G tBLEL LB, UB tEHQZ tELQX DQ0-DQ15 tEHQX VALID tELQX tEHQZ tEHQX VALID
AI07744
tEHBH
tBLEL
tEHBH
Note: 1. E2 = High and W = High. 2. Either or both LB and UB must be Low when both E1 and G are Low.
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M69AW024B
Figure 9. Address Access After G Control, Read Mode AC Waveforms
A3-A19
ADDRESS VALID
ADDRESS VALID (no change)
A0-A2
ADDRESS VALID tAVAX tAVGL1 tGLAX
ADDRESS VALID tAVGH tAXAV tAVQV tGHQZ tGHAX
E1 tGLQV G tBLGL LB, UB tGLQX DQ0-DQ15 tAXQX DATA VALID tGHQX DATA VALID tGHBH
AI07745
Note: 1. E2 = High and W = High. 2. Either or both LB and UB must be Low when both E1 and G are Low.
Figure 10. Address Access After E1 Control, Read Mode AC Waveforms
A3-A19
A0-A2
ADDRESS VALID
ADDRESS VALID tAVEH
tAVEL
tELAX
tAXAV tAVQV
tEHAX
E1 tELQV G tBLEL LB, UB tEHBH tEHQZ
tELQX DQ0-DQ15
tAXQX DATA VALID
tEHQX DATA VALID
AI07746
Note: 1. E2 = High and W = High. 2. Either or both LB and UB must be Low when both E1 and G are Low.
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M69AW024B
Table 8. Write Mode AC Characteristics
M69AW024B Symbol Alt. Parameter -60 Min tAVEL(2) tAVWL tAXGL1
(3,4)
-70 Min 0 0 Max
Unit
Max
tAS tAS tOEH tOEH(ABS) tBS tBS tDS tDS tBH tDH tWRC tCP tWH tWH tAH tCW tWRC tWC tCS tOHAH tBH tOHCL tOES tWR tBH tDH tCH tWS tWR tWC tAH
Address Set-up Time to Chip Enable Low Address Set-up Time to Write Enable Low Address Invalid to Output Enable Low Address Invalid to Output Enable Low (absolute) LB, UB Set-up Time to Chip Enable Low LB, UB Set-up Time to Write Enable Low Data Set-up Time to Chip Enable High Data Set-up Time to Write Enable High LB, UB Hold Time from Chip Enable High Input Data Hold Time from Chip Enable High Chip Enable High Pulse Width to Chip Enable Low Chip Enable High Pulse Width to Chip Enable Low Write Enable Low Hold Time Write Enable High Hold Time Address Hold Time from Chip Enable Low Chip Enable Write Pulse Width Chip Enable Write Recovery Time Chip Enable Write Cycle Time Chip Enable Write Set-up Time Address Hold Time from Output Enable High LB, UB Hold Time from Output Enable High Output Enable High to Chip Enable Low Set-up Time Output Enable Set-up Time Write Enable High to Address Valid LB, UB Hold Time from Write Enable High Input Data Hold Time from Write Enable High Chip Enable Write Hold Time Write Enable High Set-up Time Write Enable Write Recovery Time to Write Enable Low Write Enable Low to Address Valid Write Cycle Time Address Hold Time from Write Enable Low
0 0 25 12 -5 -5 15 15 -5 0 20 10 0 0 35 45 20 80 0 -5 -5 -5 0 20 -5 0 0 0 20 80 35 1000 1000 1000 1000 1000 1000
ns ns 1000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1000 ns ns ns ns 1000 1000 ns ns ns ns 1000 ns ns 1000 ns ns ns
35 15 -5 -5 20 20 -5 0 20 12 0 0 40 50 20 90 0 -5 -5 -5 0 20 -5 0 0 0 20 90 40
tAXGL2(5) tBLEL tBLWL tDVEH tDVWH tEHBH tEHDX tEHEL1(9,10) tEHEL2(10) tEHWH tEHWL tELAX(2) tELEH1(1,8) tELEH2(1,9,10) tELEL tELWL tGHAX(7) tGHBH tGHEL(6) tGHWL(3) tWHAV(1,3,9,10) tWHBH tWHDX tWHEH tWHEL tWHWL(1,3,9,10) tWLAV tWLAX(2)
17/29
M69AW024B
M69AW024B Symbol Alt. Parameter -60 Min tWLEL tWLWH(1,8) tWLWL tWS tWP tWC Write Enable Low Set-up Time Write Enable Write Pulse Width Write Enable Write Cycle Time 0 45 80 Max -70 Min 0 50 90 Max ns ns ns Unit
Note: 1. The minimum value must be equal to or greater than the sum of actual tELEH (or tWLWH). 2. The new write address is valid from either E1 High or W High. 3. tAXGL1 is specified from end of tAVAX (Min) and is a reference value when access time is determined by tAXGL1. If actual value is lower than specified minimum value, tAXGL1 is increased by the difference between the actual value and the specified minimum value. 4. tAXGL1 maximum is applicable if E1 is kept Low and both W and G are kept High. 5. tAXGL2 is the absolute minimum value if the Write cycle terminates with W and E1 Low. 6. tGHEL (Min) must be kept if the Read cycle is not performed prior to the Write cycle. In case G is disabled after a time tGHEL(Min), W must go Low tELEH2 (Min) after E1 goes Low. In other words, the Read cycle is initiated if tGHEL (Min) is not kept. 7. Applicable if E1 stays Low after the Read cycle. 8. tELEH or tWLWH is applicable if the Write operation is initiated by E1 or W, respectively. 9. If the write operation is terminated by W followed by E1 High, the sum of actual tELWL and tWLWH and the sum of actual tAVWL and tWLWH must be equal or greater than 60ns. 10. tEHEL1 or tWHWL is applicable if the Write operation is terminated by E1 or W, respectively. If E1 goes High before tWHWL (Min), then tEHEL1 (Min) must apply. 11. tEHEL1 and tEHEL2 is applicable if write operation is terminated by E1 and W, respectively. In case E1 is brought to High before satisfaction of tEHEL2 (min), the tEHEL1 (min) is also applied. 12. For other timings please refer to Table 7., Read and Standby Modes AC Characteristics.
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M69AW024B
Figure 11. E1 Controlled, Write AC Waveforms
tELEL A0-A19 tAVEL E1 tWLEL tELEH1 tEHWH W tBLEL UB, LB tGHEL G tDVEH DQ0-DQ15 VALID DATA INPUT
AI07411C
ADDRESS VALID tELAX
ADDRESS VALID tAVEL
tEHEL1 tWLEL
tEHBH
tBLEL
tEHDX
Note: 1. E2 must be High during the Write cycle.
Figure 12. W Controlled, Single Write AC Waveforms
tWLWL ADDRESS VALID A0-A19 tGHAX ADDRESS VALID tAVWL tWLAX E1 tGHEL tELWL tWLWH W tGHBH UB, LB tGHWL G tGHQZ DQ0-DQ15 tDVWH VALID DATA INPUT
AI07412C
ADDRESS VALID tAVWL tWHEH
tEHEL2 tWHWL
tBLWL
tWHBH
tWHDX
Note: 1. E2 must be High during the Write cycle.
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M69AW024B
Figure 13. W Controlled, Continuous Write AC Waveforms
tWLWL ADDRESS VALID A0-A19 tGHAX ADDRESS VALID tAVWL tWLAX E1 tGHEL tELWL tWLWH W tGHBH UB, LB tGHWL G tGHQZ DQ0-DQ15 tDVWH VALID DATA INPUT
AI07413C
ADDRESS VALID tAVWL
tWHWL
tBLWL
tWHBH
tBLWL
tWHDX
Note: 1. E2 must be High during the Write cycle.
Figure 14. E1 Controlled, Read/Write AC Waveforms
tELEL ADDRESS VALID A0-A19 tEHAX ADDRESS VALID tAVEL tELAX E1 tEHEL1 tELEH1 tEHWH tEHWL W tEHBH UB, LB tGHEL G tEHQZ tEHQX DQ0-DQ15 READ DATA OUTPUT tDVEH WRITE DATA INPUT
AI07414C
ADDRESS VALID tAVEL
tEHEL1 tWHEL ELGL
tWLEL
tBLEL
tEHBH
tBLGL
tGLQX tEHDX
Note: 1. Write address is valid from the falling edge of either E1 or W, whichever occurs later.
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M69AW024B
Figure 15. E1 Controlled, Read/Write AC Waveforms 2
tELEH A0-A19 tAVEL tEHEL1 E1 tEHEL1(min) tELQV tEHEL1 READ ADDRESS tEHAX WRITE ADDRESS tAVEL
tEHWH W tEHBH UB, LB
tWHEL
tEHWL
tWLEL
tBLEL
tEHBH
tBLEL
tELGL G
tGHEL
tEHQZ tEHDX DQ0-DQ15 WRITE DATA INPUT tELQX tEHQX READ DATA OUTPUT
AI07415C
Figure 16. G Controlled Read, W Controlled Write AC Waveforms
tWLAV ADDRESS VALID A0-A19 tGHAX WRITE ADDRESS tAVWL tWLAX E1 Low tWLWH W tGHBH UB, LB tGHWL G tGHQZ tGHQX DQ0-DQ15 READ DATA OUTPUT tDVWH WRITE DATA INPUT
AI07416C
READ ADDRESS tAVGL1
tWHAV
tBLWL
tWHBH
tBLGL
tWHDX
tGLQX
Note: 1. E1 can be tied to Low for W and G controlled operation. When E1 is tied to Low, output is exclusively controlled by G.
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M69AW024B
Figure 17. G Controlled Read, W Controlled Write AC Waveforms 2
tAVGH A0-A19 tAVGL1 E1 Low tWHAV W tWHBH UB, LB tGHWL G tGLQV tWHDX DQ0-DQ15 WRITE DATA INPUT tGLQX tGHQX READ DATA OUTPUT
AI07417C
READ ADDRESS tGHAX
WRITE ADDRESS tAVWL
tBLGL
tGHBH
tBLWL
tGHQZ
Note: 1. E1 can be tied to Low for W and G controlled operation. When E1 is tied to Low, output is exclusively controlled by G.
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M69AW024B
Table 9. Power Down and Power-Up AC Parameters
M69AW024B Symbol Alt. Parameter -60 Min tCLEL tELCH tCHEL tEHEL tEHCH1 tEHCH2 tCHCL12 tCHCL22 tEHGH tEHWH tT tCSP tC2LP tCHH tCHHP tCHS tC2LH tC2HL tCHOX tCHWX tT E2 Low Setup Time for Power Down Entry E2 Low Hold Time after Power Down Entry E1 High Hold Time following E2 High after PowerDown Exit (Sleep Mode only) E1 High Hold Time following E2 High after PowerDown Exit (not in Sleep Mode) E1 High Setup Time following E2 High after PowerDown Exit Power-up Time 1 Power-up Time 2 E1 High to G Invalid Time for Standby Entry E1 High to W Invalid Time for Standby Entry Input Transition Time 10 80 350 400 10 50 50 10 10 1 25 Max -70 Min 10 90 350 400 10 50 50 10 10 1 25 Max ns ns s s ns s s ns ns ns Unit
Note: 1. Some data may be written to any address location if tEHWH is less than the minimum required time. 2. The device has to enter and exit Power Down mode after tCHCL. 3. The Input Transition Time used in AC measurements is 5ns.
Figure 18. Standby Mode Entry AC Waveforms, After Read or Write
E1 tEHGH G
E1 tEHWH G
W
W
Active (Read)
Standby
Active (Write)
Standby
AI07741
Note: Both tEHGH and tEHWH define the earliest entry timing for Stand-by mode. If either of timing is not satisfied, it takes the tAVAX(min) period from either the last address transition of A0, A1 and A2, or E1 rising edge.
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M69AW024B
Figure 19. Power-down AC Waveforms
E1 tEHCH1 E2 tCLEL DQ Hi-Z Power Down Entry tELCH tCHEL
Power Down Mode
Power Down Exit
AI07739
Note: This Power Down mode can be also be used in "Power-up Mode AC Waveforms - 2".
Figure 20. Power-up Mode AC Waveforms - 1
E1 tEHCH1 tEHCH2 E2 tCHEL
VCC 0V
VCC min
AI07740
Note: tVHCH starts from V CC reaching VCC(min).
Figure 21. Power-up Mode AC Waveforms - 2
E1 tCHCL2 tCLEL E2 tCHCL1 VCC 0V
AI07742
tEHCH1 tELCH tCHEL
VCC min
Note: tVHCL starts from VCC reaching VCC(min). E1 must be taken High prior to, or together with, the rising edge on E2.
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M69AW024B
Figure 22. Power-up Mode AC Waveforms - 3
E1 tEHEL E2
VCC 0V
VCC min
AI08054C
Note: Both E1 and E2 must go High as VCC reaches VCC(min). If not, the timings provided in Power-Up Mode AC Waveforms 1 (Figure 20.) or Power-Up Mode AC Waveforms 2 (Figure 21.) should be used to ensure proper operation.
Table 10. Low VCC Data Retention Characteristics
Symbol VDR (2) Parameter Supply Voltage (Data Retention) Test Condition1 E1 = E2 VCC -0.2V, or E1 = VIH and E2 = VIH VCC = VDR, VIN 0.2V or VCC -0.2V, E1 = VCC -0.2V and E2 VCC -0.2V, IOUT = 0mA VCC = 2.7V VCC = 2.7V 0 100 0.2 Min 2.3 Max 3.5 Unit V
ICCDR
Supply Current (Data Retention) Chip deselected to Data Retention Time Operation Recovery Time VCC Voltage Transition Time
70
A
tCDR (2,3) tR (3) V/t (3)
ns ns V/s
Note: 1. TA = -30 to 85C 2. All other Inputs at VIH VCC -0.2V or VIL 0.2V. 3. See Figure 23. for measurement points.
Figure 23. Low VCC Data Retention AC Waveforms
VCC 3.5V 2.7V 2.3V E2
tCDR V/t
DATA RETENTION MODE V/t
tR
0.4V VSS
E1
E1 and E2 VDD - 0.2V or VIH(min) Data Bus must be Hi-Z
AI07408
25/29
M69AW024B
PACKAGE MECHANICAL
Figure 24. TFBGA48 6x8mm - 6x8 Ball Array, 0.75mm Pitch, Package Outline, Bottom View
D FD FE SD D1
SE BALL "A1" E E1 ddd
e e A A1 b A2
BGA-Z26
Note: Drawing is not to scale.
Table 11. TFBGA48 6x8mm - 6x8 Ball Array, 0.75mm Pitch, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b D D1 ddd E E1 e FD FE SD SE 8.000 5.250 0.750 1.125 1.375 0.375 0.375 7.900 - - - - - - 6.000 3.750 0.350 5.900 - 0.260 0.900 0.450 6.100 - 0.100 8.100 - - - - - - 0.3150 0.2067 0.0295 0.0443 0.0541 0.0148 0.0148 0.3110 - - - - - - 0.2362 0.1476 0.0138 0.2323 - Min Max 1.200 0.0102 0.0354 0.0177 0.2402 - 0.0039 0.3189 - - - - - - Typ Min Max 0.0472 inches
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M69AW024B
PART NUMBERING
Table 12. Ordering Information Scheme
Example: Device Type M69 = 1T/1C Memory Cell Architecture Mode A = Asynchronous Operating Voltage W = 2.7 to 3.3V Array Organization 024 = 16 Mbit (1M x16) Option 1 B = 2 Chip Enable; No Write and Standby from UB and LB Option 2 L = Low Leakage Speed Class 60 = 60ns 70 = 70ns Package ZB = TFBGA48 6x8mm - 6x8 ball array, 0.75mm pitch Temperature Range 8 = -30 to 85C Shipping Method T = Tape & Reel Packing M69AW024 B L 70 ZB 8 T
The notation used for the device number is as shown in Table 12. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest STMicroelectronics Sales Office.
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M69AW024B
REVISION HISTORY
Table 13. Document Revision History
Date 01-Jun-2002 04-Feb-2003 14-Mar-2003 29-Apr-2003 25-Jul-2003 07-May-2004 29-Sep-2004 Rev. 1.0 2.0 2.1 2.2 2.3 3.0 4.0 First Issue Document completely revised AC Testing Load Circuit revised; 60ns access time device added Timing parameter names changed in tables and illustrations Chip enable signals E1 and E2 must change together during Power-on sequence Datasheet title updated. Table 2., Operating Modes updated for read operations. Minor modification in first paragraph of Summary Description. Revision Details
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M69AW024B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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